[XEN] Clean up BASE_DISALLOW_MASK and fix for x86/64.
authorkaf24@firebug.cl.cam.ac.uk <kaf24@firebug.cl.cam.ac.uk>
Thu, 31 Aug 2006 22:44:41 +0000 (23:44 +0100)
committerkaf24@firebug.cl.cam.ac.uk <kaf24@firebug.cl.cam.ac.uk>
Thu, 31 Aug 2006 22:44:41 +0000 (23:44 +0100)
Original patch from Xiaohui Xin <xiaohui.xin@intel.com>
Signed-off-by: Keir Fraser <keir@xensource.com>
xen/include/asm-x86/page.h
xen/include/asm-x86/x86_32/page-2level.h
xen/include/asm-x86/x86_32/page-3level.h
xen/include/asm-x86/x86_32/page.h
xen/include/asm-x86/x86_64/page.h

index 01ab4be3c79e5df3e371e1ea184f6e04433779e7..905d76d57638084a773d30dc12de9708b87f817b 100644 (file)
@@ -300,13 +300,6 @@ void setup_idle_pagetable(void);
 #define _PAGE_GNTTAB   0
 #endif
 
-/*
- * Disallow unused flag bits plus PAT, PSE and GLOBAL.
- * Also disallow GNTTAB if we are using it for grant-table debugging.
- * Permit the NX bit if the hardware supports it.
- */
-#define BASE_DISALLOW_MASK ((0xFFFFF180U | _PAGE_GNTTAB) & ~_PAGE_NX)
-
 #define __PAGE_HYPERVISOR \
     (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
 #define __PAGE_HYPERVISOR_NOCACHE \
index 7f450c4624b6920c2a4563219b43efef57e626c3..e7b74dd18d507427db4b15d9645f773b1cf9b105 100644 (file)
@@ -53,7 +53,4 @@ typedef l2_pgentry_t root_pgentry_t;
 #define get_pte_flags(x) ((int)(x) & 0xFFF)
 #define put_pte_flags(x) ((intpte_t)((x) & 0xFFF))
 
-#define L1_DISALLOW_MASK BASE_DISALLOW_MASK
-#define L2_DISALLOW_MASK BASE_DISALLOW_MASK
-
 #endif /* __X86_32_PAGE_2LEVEL_H__ */
index e0187478cca0acca1ff6d63b7e7e0383dd6faa13..d7d2d19f3f3534d7b9527c1116e95f9a82c22c2a 100644 (file)
@@ -66,8 +66,6 @@ typedef l3_pgentry_t root_pgentry_t;
 #define get_pte_flags(x) (((int)((x) >> 32) & ~0xFFF) | ((int)(x) & 0xFFF))
 #define put_pte_flags(x) (((intpte_t)((x) & ~0xFFF) << 32) | ((x) & 0xFFF))
 
-#define L1_DISALLOW_MASK BASE_DISALLOW_MASK
-#define L2_DISALLOW_MASK BASE_DISALLOW_MASK
 #define L3_DISALLOW_MASK 0xFFFFF1E6U /* must-be-zero */
 
 #endif /* __X86_32_PAGE_3LEVEL_H__ */
index 78d09d1482f4e2b492f79093e2772f5a290676fb..228445a62d9ea0ada42463bccdc9be316e0ee5dd 100644 (file)
@@ -26,6 +26,15 @@ extern unsigned int PAGE_HYPERVISOR_NOCACHE;
 #define GRANT_PTE_FLAGS \
     (_PAGE_PRESENT|_PAGE_ACCESSED|_PAGE_DIRTY|_PAGE_GNTTAB)
 
+/*
+ * Disallow unused flag bits plus PAT, PSE and GLOBAL.
+ * Permit the NX bit if the hardware supports it.
+ */
+#define BASE_DISALLOW_MASK (0xFFFFF180U & ~_PAGE_NX)
+
+#define L1_DISALLOW_MASK (BASE_DISALLOW_MASK | _PAGE_GNTTAB)
+#define L2_DISALLOW_MASK (BASE_DISALLOW_MASK)
+
 #endif /* __X86_32_PAGE_H__ */
 
 /*
index 429cfb8c5d3af91599feea9c0e4df7d13e678835..d323362be92b70f715bd1e839955cc0b6cb73285 100644 (file)
@@ -75,8 +75,15 @@ typedef l4_pgentry_t root_pgentry_t;
 #define _PAGE_NX_BIT (1U<<23)
 #define _PAGE_NX     (cpu_has_nx ? _PAGE_NX_BIT : 0U)
 
-#define L1_DISALLOW_MASK BASE_DISALLOW_MASK
-#define L2_DISALLOW_MASK BASE_DISALLOW_MASK
+/*
+ * Disallow unused flag bits plus PAT, PSE and GLOBAL.
+ * Permit the NX bit if the hardware supports it.
+ * Note that range [62:52] is available for software use on x86/64.
+ */
+#define BASE_DISALLOW_MASK (0xFF000180U & ~_PAGE_NX)
+
+#define L1_DISALLOW_MASK (BASE_DISALLOW_MASK | _PAGE_GNTTAB)
+#define L2_DISALLOW_MASK (BASE_DISALLOW_MASK)
 #define L3_DISALLOW_MASK (BASE_DISALLOW_MASK | 0x180U /* must-be-zero */)
 #define L4_DISALLOW_MASK (BASE_DISALLOW_MASK | 0x180U /* must-be-zero */)